This application claims priority to Korean Patent Application No. 2002-49132, filed on Aug. 20, 2002, which is incorporated herein by reference.
The present invention is related to integrated circuit devices, and in particular to a device and method for varying the period or frequency of a clock signal according to current consumption.
The use of various integrated circuit devices with portable equipment has become widespread. These integrated circuit devices are referred to as xe2x80x9cembedded system chipsxe2x80x9d or xe2x80x9cembedded chipsxe2x80x9d. An embedded chip is supplied with voltage from a power supply of the portable equipment, which is typically some form of battery. To conserve battery power, low-power operation is typically a requirement for such equipment. The amount of power consumption is primarily based on the given application(s). For example, clock speed is one significant factor that is used to determine the power consumption in an embedded system chip. Since embedded chips operate in synchronization with a clock, power consumption increases in proportion to an increase of the clock speed and power consumption decreases in proportion to a decrease of the clock speed. Therefore, for a low-power system, it is a general design criteria to limit the electric power consumption via limitation of the clock speed.
Typically, a plurality of different functional blocks (components, devices, circuits, etc.) are included in an embedded system chip. In general, an operable clock speed and power consumption are pre-specified for all functional blocks or embedded system chips. More specifically, to obtain the maximum performance of a chip within the maximum power range determined in a specification, the design of an optimized clock speed is significantly considered when designing an embedded system chip or a system. In case of an embedded system chip or a functional block where the power consumption affects its operating performance, a simple and generalized design method is as follows: (i) determine the power when operating a functional block having the largest power consumption; (ii) determine a clock as an internal clock, when the determined power is a maximum allowed power; and (iii) design other functional blocks (or embedded system chips) on the basis of the determined clock.
This conventional design method described above, however, has a disadvantage in that the operating performance is sub-optimal due to the fixed clock speed which is applied even with a functional block (or system) whose current consumption is relatively less.
The present invention is directed to circuits and methods for optimizing operating performance of an integrated circuit device within a maximum allowed current by varying a period of a clock signal based on an amount of current consumed by the integrated circuit device.
In accordance with one aspect of the invention, an integrated circuit device comprises a plurality of functional blocks each operating in synchronization with a clock signal, a power supply line that supplies an internal power supply voltage to the functional blocks, a charge storing means connected to the power supply line, a comparator circuit that compares a voltage on the power supply line with a reference voltage and generates a control voltage based on the result of the comparison, a charge supplying means that supplies charges from an external power supply voltage to the power supply line in response to the control voltage, and a clock generator circuit that generates a clock signal in response to the control voltage, wherein the period of the clock signal varies according to variation of the control voltage.
Preferably, when the control voltage increases, the period of the clock signal increases, and when the control voltage decreases, the period of the clock signal decreases.
In another aspect of the invention, the charge supplying means comprises a PMOS transistor that is connected between the external power supply voltage and the power supply line, and which is controlled by the control voltage. The charge storing means preferably comprises a capacitor connected between the power supply line and ground.
In yet another aspect of the invention, the clock generator circuit comprises a first means for generating second control voltage that varies according to variation of the control voltage, and a second means for generating the clock signal whose period varies according to variation of the second control voltage. Preferably, the first means comprises a PMOS transistor, which is connected between the external power supply voltage and an output node, for outputting the second control voltage, and an NMOS transistor, which is connected between the output node and ground, and which operates responsive to the second control voltage.
In another aspect of the invention, the second means for generating a clock signal comprises a plurality of inverters which are connected in series to the clock signal, a plurality of capacitors which are connected between output terminals of the inverters and ground, and a plurality of NMOS transistors which are connected between the output terminals of the inverters and the capacitors, wherein the NMOS transistors are controlled in common by the second control voltage.
In yet another aspect of the invention, the second means for generating a clock signal comprises a clock generator that generates a plurality of clock signals in response to a reference clock signal, each of the clock signals having different periods from each other, a signal generator that generates select signals in response to the second control voltage, and a selector that selects one of the clock signals in response to the select signals, wherein the selected clock signal is applied to the functional blocks as a clock signal.
In another aspect of the invention, a method for optimizing the operating performance of an integrated circuit device, which includes a plurality of functional blocks, comprises the steps of detecting an amount of current consumed by the integrated circuit device, controlling an amount of current supplied to the functional blocks based on the detected current consumption, and adjusting a period of a clock signal applied to the functional blocks based on the detected current consumption.